In radar signal processing, various computations must be performed on large amounts of data in order to produce the desired processed signals representative of the environment of the radar system. In many cases, the results of a first computation must be available before a second computation can begin. It is impractical to make hardware connections of a sufficient number of signal processors to perform all the desired computations simultaneously, or in a pipeline, as hundreds or thousands of interconnected processors might be required. Consequently, digital signal processing for radar systems has relied on a few fast processors, which perform the many computations in a time-sequential or hierarchical manner.
The design of such digital signal processors for high throughput, high operating speed, and proper operation is one which admits of many possible solutions. An improved radar signal processor is desired.